T5-E1-IPEX Modules

This topic is intended to provide hardware information and serve as a reference when you develop with T5-E1-IPEX modules. It helps you get an overall understanding of the product specifications and assists in developing products and applications.

Overview

T5-E1-IPEX is a highly integrated single-antenna single-band 2.4 GHz Wi-Fi 6 (IEEE 802.11b/g/n/ax) and Bluetooth 5.4 Low Energy (LE) combo IoT module. Featuring a multi-peripheral packaging and ultra-low-power chip, the T5-E1-IPEX module provides a highly integrated, efficient, secure, and lowest-power environment for IP cameras, HMI applications, smart locks, and other advanced IoT applications.

The T5-E1-IPEX module is embedded with an ARMv8-M Star (M33F) processor with a clock rate of up to 480 MHz, and integrates 8 MB flash memory, 16 MB PSRAM, 640 KB SRAM shared memory, and 64 KB ROM. Support interfaces such as USB, UART, SDIO, SPI, I2C, I2S, and ADC, as well as external devices such as displays, cameras, microphones, speakers, and microSD cards.

Appearance

Pins on module

T5-E1-IPEX is equipped with a total of 70 pins, including 40 LCC pins and 30 LGA pins.

The pinout is as follows:

No.	Name	I/O type	Features
1	GND	P	Ground pin
2	3V3	P	Power pin
3	RST	I	The low-level reset pin, active high, and pulled up internally
4	P20	I/O	GPIO20 I2C0_SCL SWCLK RGB_R6 I8080_D9 SEG10
5	P21	I/O	I2C0_SDA SWDIO ADC6 RGB_R5 I8080_D8 SEG9
6	P22	I/O	CLK26M PWMG0_PWM2 ADC5 QSPI0_SCK RGB_R4 I8080_CSX SEG8
7	P23	I/O	PWMG0_PWM3 ADC3 QSPI0_CS RGB_R3 I8080_RESET SEG7
8	P24	I/O	LPO_CLK PWMG0_PWM4 ADC2 QSPI0_IO0 RGB_G7 I8080_RSX SEG6
9	P25	I/O	IRDA PWMG0_PWM5 ADC1 QSPI0_IO1 RGB_G6 I8080_WRX SEG5
10	P26	I/O	QSPI0_IO2 RGB_G5 I8080_RDX SEG4
11	P28	I/O	I2S_MCLK ADC4 TOUCH2 CLK_AUXS_CIS SEG18
12	P1	I/O	UART1_RX I2C1_SDA SWDIO SC_CLK ADC13 LIN_RXD
13	DN	I/O	USB D-
14	DP	I/O	USB D+
15	P0	I/O	UART1_TX I2C1_SCL SWCLK SC_IO ADC12 LIN_TXD
16	P9	I/O	PWMG0_PWM3 I2S0_DOUT DMIC_DAT 32K_XI
17	P8	I/O	PWMG0_PWM2 I2S0_DIN DMIC_CLK ADC10 32K_XO
18	P7	I/O	PWMG0_PWM1 I2S0_SYNC QSPI1_IO3
19	P6	I/O	PWMG0_PWM0 I2S0_SCK QSPI1_IO2
20	P5	I/O	SPI1_MISO SDIO_DATA1 COM7 QSPI1_IO1 SEG31
21	P4	I/O	SPI1_MOSI SDIO_DATA0 COM6 QSPI1_IO0 SEG30
22	P3	I/O	SPI1_CSN SDIO_CMD SC_VCC QSPI1_CS
23	P2	I/O	SPI1_SCK SDIO_CLK SC_RSTN LIN_SLEEP QSPI1_SCK
24	P12	I/O	UART0_RTS TOUCH0 ADC14
25	P13	I/O	UART0_CTS TOUCH1 ADC15
26	P15	I/O	SDIO_CMD SPI0_CSN I2C1_SDA RGB_DISP I8080_D14 SEG15
27	P14	I/O	SDIO_CLK SPI0_SCK I2C1_SCL RGB_DCLK I8080_D15 SEG16
28	P16	I/O	SDIO_DATA0 SPI0_MOSI RGB_DE I8080_D13 SEG14
29	P17	I/O	SDIO_DATA1 SPI0_MISO RGB_HSYNC I8080_D12 SEG13
30	P18	I/O	SDIO_DATA2 PWMG0_PWM0 RGB_VSYNC I8080_D11 SEG12
31	P19	I/O	SDIO_DATA3 PWMG0_PWM1 RGB_R7 I8080_D10 SEG11
32	P47	I/O	SPI0_MISO ENET_MDC TOUCH15 RGB_B3 I8080_D0 COM0 I2S2_DOUT
33	P46	I/O	CAN_STBY SPI0_MOSI ENET_PHY_INT TOUCH14 RGB_B4 I8080_D1 COM1 I2S2_DIN
34	P45	I/O	CAN_RX SPI0_CSN RGB_B5 I8080_D2 COM2 I2S2_SYNC
35	P44	I/O	CAN_TX SPI0_SCK RGB_B6 I8080_D3 COM3 I2S2_SCK
36	RXD	I/O	DL_UART_RX SDIO_DATA2 CLK_AUXS_CIS UART0_RX The pin to flash firmware and authorize modules
37	TXD	I/O	DL_UART_TX UART0_TX SDIO_DATA3 The pin to flash firmware and authorize modules
38	P43	I/O	I2C1_SDA I2S1_DOUT SC_VCC RGB_B7 I8080_D4 SEG0
39	P42	I/O	I2C1_SCL I2S1_DIN LIN_SLEEP SC_RSTN RGB_G2 I8080_D5 SEG1
40	GND	P	Ground pin
41	P27	I/O	CIS_MCLK CLK_AUXS_CIS ENET_PHY_INT QSPI0_IO3 SEG17
42	P29	I/O	CIS_PCLK ENET_MDC TOUCH3 SEG19
43	P50	I/O	ENET_RXD1 RGB_R0
44	P49	I/O	ENET_RXD0 RGB_R1 I8080_D17
45	P41	I/O	UART2_TX I2S1_SYNC LIN_TXD SC_IO RGB_G3 I8080_D6 SEG2
46	P31	I/O	CIS_VSYNC UART2_TX LIN_TXD TOUCH5 SC_IO SEG21
47	P30	I/O	CIS_HSYNC UART2_RX LIN_RXD TOUCH4 SC_CLK SEG20
48	P33	I/O	CIS_PXD1 PWMG1_PWM1 ENET_RXD0 TOUCH7 TOUCH7 SEG23
49	P32	I/O	CIS_PXD0 PWMG1_PWM0 ENET_MDIO TOUCH6 SC_RSTN SEG22
50	P48	I/O	ENET_MDIO RGB_R2 I8080_D16
51	P34	I/O	CIS_PXD2 PWMG1_PWM2 ENET_RXD1 TOUCH8 SPI0_CSN SEG24
52	P35	I/O	CIS_PXD3 PWMG1_PWM3 ENET_RXDV TOUCH9 SPI0_MOSI SEG25
53	P53	I/O	ENET_TXD1 RGB_B2
54	P54	I/O	ENET_TXEN RGB_B1
55	P55	I/O	ENET_REF_CLK RGB_B0
56	P36	I/O	CIS_PXD4 PWMG1_PWM4 ENET_TXD0 TOUCH10 SPI0_MISO SEG26
57	P37	I/O	CIS_PXD5 PWMG1_PWM5 ENET_TXD1 TOUCH11 SEG27
58	P52	I/O	ENET_TXD0 RGB_G0
59	P51	I/O	ENET_RXDV RGB_G1
60	GND	P	Ground pin
61	LN	AO	Audio left channel negative output
62	LP	AO	Audio left channel positive output
63	P38	I/O	CIS_PXD6 I2C1_SCL ENET_TXEN TOUCH12 COM4 SEG28
64	P39	I/O	CIS_PXD7 I2C1_SDA ENET_REF_CLK TOUCH13 COM5 SEG29
65	P40	I/O	UART2_RX I2S1_SCK LIN_RXD SC_CLK RGB_G4 I8080_D7 SEG3
66	MP1	AO	Microphone 1 positive input
67	MN1	AO	Microphone 1 negative input
68	MN2	AO	Microphone 2 negative input
69	MP2	AO	Microphone 2 positive input
70	MBS	AO	Microphone bias output

API description

UART

Pin description

The module provides three UART interfaces:

• UART 0: used to connect to your MCU. The serial data transmission follows Tuya’s protocol. The baud rate is 115200 bps by default.

• UART 1: used to connect to peripheral devices.

• UART 2: used to connect to peripheral devices.

  Pin No.	Signal	Feature description
  36	DL_UART_RX	UART 0. It can be used as a download port to receive data.
  37	DL_UART_TX	UART 0. It can be used as a download port to transmit data.
  12	UART1_RX	UART 1 to receive data.
  15	UART1_TX	UART 1 to transmit data.
  45	UART2_TX	UART 2 to transmit data.
  65	UART2_RX	UART 2 to receive data.

Serial communication between module and MCU

• Connection between a module and a 3.3V MCU

  

• Connection between a module and a 5V MCU

  In the following circuit diagram, voltage level translation can be implemented with a bidirectional voltage-level translator, a MOS transistor, or a triode.

  

Level translator reference

• N-channel MOSFET level translator: An N-channel MOSFET and a built-in body diode are used to implement two-way communication.

  

• NPN triode level translator: An NPN triode is used to implement one-way communication.

  

  See the circuit diagram above for how UART 1, UART 2, and UART 0 are connected.

Circuit design

The UART trace should be as short as possible. Add ground vias around the UART and keep away from RF and periodic signal lines.

USB

Pin description

The USB interface conforms to USB 2.0 specifications.

Pin No.	Signal	Feature description
13	USB_DN	USB high-speed differential transceiver (negative). It can be used to download code to the module.
14	USB_DP	USB high-speed differential transceiver (positive). It can be used to download code to the module.

Applications

• MCU solutions

  

• Micro-USB cable

  

Circuit design

• Make sure to route the USB signal traces as differential pairs with total grounding, keeping them parallel and of equal length. The impedance of the USB differential trace is 90Ω.
• Do not route signal traces under the power supply, RF signal traces, and other sensitive signal traces. It is important to route the USB differential traces in the inner layer with ground shielding on not only the upper and lower layers but also the right and left sides.
• Connect a common mode choke between the MCU and module in series to improve EMI suppression.
• Considering the connection to micro-USB devices, place the TVS diode as close to the USB port as possible with a parasitic capacitance of less than 2 pF.

SPI

The T5-E1-IPEX module has two sets of SPI interfaces, and the following table details the pins:

Pin No.	Signal	Feature description
26	SPI0_CSN	GPIO15, SPI0 chip select signal
28	SPI0_MOSI	GPIO16, SPI0 controller out and agent in
29	SPI0_MISO	GPIO17, SPI0 controller in and agent out
27	SPI0_SCK	GPIO14, SPI0 clock signal
22	SPI1_CSN	GPIO3, SPI1 chip select signal
21	SPI1_MOSI	GPIO4, SPI1 controller out and agent in
20	SPI1_MISO	GPIO5, SPI1 controller in and agent out
23	SPI1_SCK	GPIO2, SPI1 clock signal

Electrical specifications and applications

The voltage level of the SPI interface on this module is 3.3V. A level translator should be used if the application is equipped with a 5V UART interface. A level translator for SPI is recommended.

The reference circuit is shown in the figure below:

QSPI

The T5-E1-IPEX module has two sets of QSPI interfaces, and the following table details the pins:

Pin No.	Signal	Feature description
6	QSPI0_SCK	GPIO22, QSPI0 clock signal
7	QSPI0_CS	GPIO23, QSPI0 enable signal
8	QSPI0_IO0	GPIO24, QSPI0 data bit 0
9	QSPI0_IO1	GPIO25, QSPI0 data bit 1
10	QSPI0_IO2	GPIO26, QSPI0 data bit 2
41	QSPI0_IO3	GPIO27, QSPI0 data bit 3
18	QSPI1_IO3	GPIO7, QSPI1 data bit 3
19	QSPI1_IO2	GPIO6, QSPI1 data bit 2
20	QSPI1_IO1	GPIO5, QSPI1 data bit 1
21	QSPI1_IO0	GPIO4, QSPI1 data bit 0
22	QSPI1_CS	GPIO3, QSPI1 enable signal
23	QSPI1_SCK	GPIO2, QSPI1 clock signal

I2C

The T5-E1-IPEX module has two sets of I2C interfaces, and the following table details the pins:

Pin No.	Signal	Feature description
4	I2C0_SCL	GPIO20, I2C0 clock signal
5	I2C0_SDA	GPIO21, I2C0 data signal
15	I2C1_SCL	GPIO0, I2C1 clock signal
12	I2C1_SDA	GPIO1, I2C1 data signal

I2C is a simple serial communication bus protocol that uses just two bus wires, a serial data wire (SDA) and a serial clock wire (SCL). I2C is integrated into many ICs and allows devices to communicate directly with each other. Each device is recognized by a unique address to differentiate from other devices on the same I2C bus and can operate either as a transmitter or a receiver depending on its function.

Applications

The I2C bus must be pulled up on the device.

I2S

The T5-E1-IPEX module has three sets of I2S interfaces, and the following table details the pins:

Pin No.	Signal	Feature description
11	I2S_MCLK	GPIO28, main clock signal
16	I2S0_DOUT	GPIO9, I2S0 output signal
17	I2S0_DIN	GPIO8, I2S0 input signal
18	I2S0_SYNC	GPIO7, I2S0 sync signal
19	I2S0_SCK	GPIO6, I2S0 clock signal
32	I2S2_DOUT	GPIO47, I2S2 output signal
33	I2S2_DIN	GPIO46, I2S2 input signal
34	I2S2_SYNC	GPIO45, I2S2 sync signal
35	I2S2_SCK	GPIO44, I2S2 clock signal
38	I2S1_DOUT	GPIO43, I2S1 output signal
39	I2S1_DIN	GPIO42, I2S1 input signal
45	I2S1_SYNC	GPIO41, I2S1 sync signal
65	I2S1_SCK	GPIO40, I2S1 clock signal

SDIO

The T5-E1-IPEX module has one set of SDIO interfaces, and the following table details the pins:

Pin No.	Signal	Feature description
20/29	SDIO_DATA1	GPIO5/GPIO17, SDIO data bit 1
21/28	SDIO_DATA0	GPIO4/GPIO16, SDIO data bit 0
22/26	SDIO_CMD	GPIO3/GPIO15, SDIO command
23/27	SDIO_CLK	GPIO2/GPIO14, SDIO clock
30/36	SDIO_DATA2	GPIO18/UART0_RX, SDIO data bit 2
31/37	SDIO_DATA3	GPIO19/UART0_TX, SDIO data bit 3

Applications

Circuit design

• Reserve a 22Ω resistor between the SD_CLK and SD signal trace in series to reduce RF interference.
• Reserve a pad for 0201 33 pF capacitor on the SD signal trace.
• SD_DATA[0:3] and SD_CMD have reserved pull-up resistors to increase bus stability.
• The SD_CLK signal trace needs ground shielding individually. Its length should be as short as possible, within 2,500 mil, preferably within 2,000 mil. Surround SD signal traces with total grounding to prevent any possible crosstalk and noise coupling from other signal sources.
• It is recommended to keep the same trace length for SD_CLK, SD_DATA[0:3], and SD_CMD, with a length difference of less than 1 mm. The total length should not exceed 50 mm.
• In order to offer good ESD protection, it is recommended to add an ESD diode array with a parasitic capacitance of less than 15 pF. The ESD protection device should be placed as close as possible to the SIM card connector 3V3, SD_CLK, SD_DATA[0:3], and SD_CMD. Make sure the SIM card signal lines go through the ESD protection device first and then to the module.

Camera

Pin description

Pin No.	Signal	Feature description
41	CIS_MCLK	GPIO27, driver clock that is output to the sensor
42	CIS_PCLK	GPIO29, pixel clock
46	CIS_VSYNC	GPIO31, frame sync signal
47	CIS_HSYNC	GPIO30, horizontal sync signal
48	CIS_PXD1	GPIO33, pixel data, data bit 1
49	CIS_PXD0	GPIO32, pixel data, data bit 0
51	CIS_PXD2	GPIO34, pixel data, data bit 2
52	CIS_PXD3	GPIO35, pixel data, data bit 3
56	CIS_PXD4	GPIO36, pixel data, data bit 4
57	CIS_PXD5	GPIO37, pixel data, data bit 5
63	CIS_PXD6	GPIO38, pixel data, data bit 6
64	CIS_PXD7	GPIO39, pixel data, data bit 7

Applications

RGB888

Pin description

Pin No.	Signal	Feature description
31	RGB_R7	GPIO 19, RGB red component data bit 7
4	RGB_R6	GPIO 20, RGB red component data bit 6
5	RGB_R5	GPIO 21, RGB red component data bit 5
6	RGB_R4	GPIO 22, RGB red component data bit 4
7	RGB_R3	GPIO 23, RGB red component data bit 3
50	RGB_R2	GPIO 48, RGB red component data bit 2
44	RGB_R1	GPIO 49, RGB red component data bit 1
43	RGB_R0	GPIO 50, RGB red component data bit 0
8	RGB_G7	GPIO 24, RGB green component data bit 7
9	RGB_G6	GPIO 25, RGB green component data bit 6
10	RGB_G5	GPIO 26, RGB green component data bit 5
65	RGB_G4	GPIO 40, RGB green component data bit 4
45	RGB_G3	GPIO 41, RGB green component data bit 3
39	RGB_G2	GPIO 42, RGB green component data bit 2
59	RGB_G1	GPIO 51, RGB green component data bit 1
58	RGB_G0	GPIO 52, RGB green component data bit 0
38	RGB_B7	GPIO 43, RGB blue component data bit 7
35	RGB_B6	GPIO 44, RGB blue component data bit 6
34	RGB_B5	GPIO 45, RGB blue component data bit 5
33	RGB_B4	GPIO 46, RGB blue component data bit 4
32	RGB_B3	GPIO 47, RGB blue component data bit 3
53	RGB_B2	GPIO 53, RGB blue component data bit 2
54	RGB_B1	GPIO 54, RGB blue component data bit 1
55	RGB_B0	GPIO 55, RGB blue component data bit 0
27	RGB_DCLK	GPIO 14, clock signal
26	RGB_DISP	GPIO 15, display on/off
29	RGB_HSYNC	GPIO 17, horizontal sync signal
30	RGB_VSYNC	GPIO 18, vertical sync signal
28	RGB_DE	GPIO 16, data enable signal

Ethernet

Pin description

Pin No.	Signal	Feature description
41	ENET_PHY_INT	GPIO 27, interrupt signal
42	ENET_MDC	GPIO 29, bus clock signal
48	ENET_RXD0	GPIO 33, data receiving signal, bit 0
49	ENET_MDIO	GPIO 32, management data input and output signals
51	ENET_RXD1	GPIO 34, data receiving signal, bit 1
52	ENET_RXDV	GPIO 35, data receiving valid signal
56	ENET_TXD0	GPIO 36, data sending signal, bit 0
57	ENET_TXD1	GPIO 37, data sending signal, bit 1
63	ENET_TXEN	GPIO 38, data sending enable signal
64	ENET_REF_CLK	GPIO 39, reference clock signal

Applications

Touch

The T5-E1-IPEX module provides 16 capacitive sensing GPIOs, and the following table details the pins:

Pin No.	Signal	Feature description
11	P28	TOUCH2
24	P12	TOUCH0
25	P13	TOUCH1
32	P47	TOUCH15
33	P46	TOUCH14
42	P29	TOUCH3
46	P31	TOUCH5
47	P30	TOUCH4
48	P33	TOUCH7
49	P32	TOUCH6
51	P34	TOUCH8
52	P35	TOUCH9
56	P36	TOUCH10
57	P37	TOUCH11
63	P38	TOUCH12
64	P39	TOUCH13

• When using the touch feature, it is recommended to reserve a series resistor close to the module to reduce coupling noise and interference on the line and to enhance ESD protection. The recommended resistance value is 470 Ω to 2 kΩ, with 510 Ω preferred. The specific value depends on the actual test results of the product.

• The traces should be as short and thin as possible, with a length less than 300 mm, a width no greater than 0.18 mm, and a trace angle greater than or equal to 90°. The spacing between different touch channels should be as far as possible, and they should be away from RF, I2C, SPI, and high-speed signal lines.

• The touch electrodes and traces are surrounded by a grid ground, and the trace clearance from the ground ranges from 0.5 mm to 1 mm.

• The diameter of the touch electrodes ranges from 8 mm to 15 mm.

  

Speaker

Pin description

Pin No.	Signal	Feature description
61	LN	AUDL_N, audio negative output
62	LP	AUDL_P, audio positive output

Applications

MIC

Pin description

Pin No.	Signal	Feature description
66	MP1	MIC1_P, positive input of microphone 1
67	MN1	MIC1_N, negative input of microphone 1
68	MN2	MIC2_N, negative input of microphone 2
69	MP2	MIC2_P, positive input of microphone 2
70	MBS	MICBIAS, microphone bias voltage

Applications

Power supply

• The operating voltage range of the T5-E1-IPEX module is 2.0V to 3.6V, with a typical value of 3.3V. The supply current for 3.3V modules must be greater than the maximum input current. The total capacity of the external filter capacitor should be greater than 10 μF.
• Place the filter capacitors C1 and C2 near the power pin of the module.

Pins of the module

• The GPIO might experience an uncontrollable high level within five milliseconds of starting the module (before the program startup). Place a 4.7 kΩ pull-down resistor if needed.
• The RST pin of the module is a hardware reset pin. The module has internal weak pull-up resistors configured. If the pin is not used, it can float. If a module has been paired, this pin cannot be used to clear pairing information.
• The TX1 pin on the module is used to select a mode. Pulling TX1 down before the module is powered on will start the test firmware, while floating it or pulling it up will start the application firmware. In normal use, this pin is used as a log printing port.
• Other unused pins can be left floating.
• For more information about pin configuration, see the module datasheet.

Power-on sequence of the module

• Suppose that the high-level voltage settling time of the module’s GPIO is t2 and the voltage settling time of the module power pin is t1. Every time the module is powered on, t2 must be greater than or equal to t1. As shown in the following figure:

  

• If t2 is less than t1, the module might fail to start.

  • To return the module to its normal state, pull down the module reset pin (RST) for one millisecond and pull up to restart the module.
  • Repeatedly power cycling the module power pin will not restore it to its normal state.

Low power design

Option 1: Control module power pin on/off

This circuit design can achieve overall low power consumption.

• How it works: As shown in the circuit diagram, the MCU can control the switch S1 with the GPIO pin to power on/off the module.

  • When the MCU has data to report to the cloud, it turns the S1 on. Then, the module can receive data from the MCU and report data to the cloud and the mobile app.
  • When data reporting is completed, the module will be powered off and consume no power.

• Disadvantages:

  1. Current sinking occurs. When the switch S1 is turned off, the TXD and RXD pins on the module are still connected to the RXD and TXD pins on the MCU.
  2. Therefore, the current from the MCU can flow into the VCC pin of the module through the UART pin.
  3. The TXD and RXD pins of the module are high, so the current sinking will increase the consumption of the module.
  4. When the switch S1 is turned on next time, t2 will be less than t1, which can cause the module to be frozen.

• Solution 1: Optimize the software of the MCU without hardware modification. When the MCU detects the data reporting is completed, the program proceeds with the following steps.

  1. Set the TXD and RXD pins of the MCU as GPIO pins that are configured as the open-drain or weak pull-down mode.
  2. Turn the switch S1 off to power off the module.
  3. This way, when the MCU has data to report, it turns the S1 on firstly.
  4. Then, it configures the TXD and RXD pins as the UART to establish communication with the module for data transmission.
  This solution does not apply to MCUs whose UART pin cannot be configured as the open-drain or weak pull-up mode. If the UART circuit has a pull-up resistor, one terminal of the resistor must be connected to the VCC pin of the module, or you can directly remove this resistor.

• Solution 2: Add a level translator to the circuit without software modification. See the circuit diagram in the preceding sections Level translator reference and Connection between a module and a 3.3V MCU and embed a level translator in the UART circuit.

Option 2: Reduce power usage in idle state

Pull down the module’s RST pin to reduce idle consumption.

• How it works: As shown in the circuit diagram, the MCU can control the RST pin with the GPIO pin to power on/off the module.

  • When the MCU has data to report to the cloud, the GPIO outputs high to power on the module. Then, the module can receive data from the MCU and report data to the cloud and the mobile app.
  • When data reporting is completed, the GPIO outputs low and the module runs in reset mode with low power consumption.

• Disadvantage: The RST pin has a 10 kΩ internal pull-up resistor, so the module has an input current of 330 μA in the reset mode.

Radio frequency (RF) test

The antenna is susceptible to the distance from the shell to the surrounding components. We recommend that you test the RF performance after the final test. The RF test items and metrics are listed in the following table.

Test item	Test metric
Increasing indoor distance	≥ 50m
Increasing outdoor distance	≥ 75m
Total radiated power (TRP) in the signaling mode of end devices (test mode of 11B 11 Mbit/s).	≥ 10 dBm
Total isotropic sensitivity (TIS) in the signaling mode of end devices (test mode of 11B 11 Mbit/s).	≤ -83 dBm

Antenna

Antenna clearance

• Do not use metal shells or plastic shells with metallic paint or coating in the direction of the antenna radiation. Do not use metal objects such as screws and rivets near the antenna, which might affect the antenna efficiency. The distance between the antenna and other mental components should be at least 15 mm.

• Try to increase the distance from the upper and bottom shells to the antenna to minimize the impact on antenna performance.

• Keep the module away from speakers, power switches, cameras, HDMI, USB, and other high-speed signals to avoid interference.

• Avoid metal shielding near the antenna. If co-channel interference occurs, you must evaluate the impact on the antenna performance and ensure isolation from interference.

Packing and manufacturing

Mechanical dimensions and backside pad dimensions

SMT package