S130N-ISI Module Datasheet

Overview

The S130N-ISI module is a fully integrated power line communication (PLC) module based on Unicomsemi VC6330 chip design. It incorporates a 32-bit ARM Cortex-M3 MCU, 32-bit DSP, embedded flash memory, 1 MB SRAM, and abundant communication interfaces.

The module adopts an LCC package design, featuring ultra-compact dimensions and a highly integrated structure. With built-in line drivers, it delivers low power consumption and excellent noise immunity. This solution is ideally suited for various PLC real-time communication applications, including smart street lighting, smart home systems, central air conditioning, and ubiquitous electrical IoT edge devices.

Description

Features

• CPU and storage:

  • 32-bit ARM Cortex-M4 MCU with 32-bit DSP
  • 2 MB on-chip flash memory
  • 1 MB on-chip SRAM

• PLC PHY

  • Support 0 to 12 MHz bandwidth (SGCC standard) with multiple available sub-bands
  • Comply with China SGCC Q/GDW 11612 protocol
  • Comply with IEEE 1901.1 protocol
  • Support modulation schemes: BPSK, QPSK, and 16QAM

• Peripheral interfaces

  • UART interface, GPIO interface, PWM/EPWM output, ADC input, SPI interface, and I2C interface

Block diagram

The following figure shows a typical application circuit:

Pin definition

Module appearance

Pinout

Pin features

Hardware design

Input power requirements

• The maximum value in the table represents the module’s maximum tolerance limit. Exceeding this value might damage the module.
• Put at least one 10 μF ground storage capacitor and one 0.1 μF decoupling capacitor near the module’s 3.3V pin. This way, reduce the power supply ripple voltage, and keep peak-to-peak ripple within 100 mV.
• Provide an independent 3.3V power supply for the module whenever possible. When sharing a 3.3V power supply with other modules on the motherboard, please use 600R/100MHz magnetic beads with a current resistance of 1A or above for isolation.
• The 3.3V power supply should ensure a current of at least 300 mA.
• Ensure proper ground return path design in PCB layout.

Suggestions on I/O design

• For interfaces such as GPIO, PWM, EPWM, and ADC, connect a 56Ω damping resistor in series and place it close to the module. For I/O pull-up and pull-down requirements, refer to the pin definition. If it is unused, leave it floating.
• EPWM1_A and EPWM1_B form a complementary ePWM pair with synchronized frequency. The same applies to EPWM2_A and EPWM2_B, EPWM3_A and EPWM3_B, as well as EPWM5_A and EPWM5_B. When different EPWM frequencies are required, only one signal (either A or B) from each complementary pair can be used.

Typical networking diagram of CCO and STA

Reference dimensions

Package dimensions

Unit: mm.

Module label

The shipped module comes with a QR code label containing the following information:

Critical materials

Ordering information

Recommended oven temperature curve

Packaging

Blister packaging

Moisture sensitivity

According to IPC/JEDEC J-STD-020 standards, the module is classified as a Moisture Sensitivity Level 3 (MSL 3) device. Please observe all relevant handling requirements and exercise caution during use.

Additionally, you must pay attention to the following points:

• Shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH).
• Production environment conditions: ≤30°C/60% RH as per IPC/JEDEC J-STD-033A Section 5. Baking is required if conditions are unmet.
• Maximum exposure time: <168 hours between sealed bag opening and reflow process. Baking is required if conditions are unmet.
• Compliance: Adhere to IPC/JEDEC J-STD-033A Section 5.2.
• Humidity indicator: Baking is required if the humidity indicator in the bag shows ≥10% RH.